Special opcodes always have their lower five bits unset, have one value and a five bit opcode. In binary, they have the format: aaaaaaooooo00000 The value (a) is in the same six bit format as defined earlier.
| C | VAL | NAME | DESCRIPTION |
|---|---|---|---|
| - | 0x00 | n/a | reserved for future expansion |
| 3 | 0x01 | JSR a | pushes the address of the next instruction to the stack, |
| then sets PC to a | |||
| - | 0x02 | - | |
| - | 0x03 | - | |
| - | 0x04 | - | |
| - | 0x05 | - | |
| - | 0x06 | - | |
| - | 0x07 | - | |
| 4 | 0x08 | INT a | triggers a software interrupt with message a |
| 1 | 0x09 | IAG a | sets a to IA |
| 1 | 0x0a | IAS a | sets IA to a |
| 3 | 0x0b | RFI a | disables interrupt queueing, pops A from the stack, then |
| pops PC from the stack | |||
| 2 | 0x0c | IAQ a | if a is nonzero, interrupts will be added to the queue |
| instead of triggered. if a is zero, interrupts will be | |||
| triggered as normal again | |||
| - | 0x0d | - | |
| - | 0x0e | - | |
| - | 0x0f | - | |
| 2 | 0x10 | HWN a | sets a to number of connected hardware devices |
| 4 | 0x11 | HWQ a | sets A, B, C, X, Y registers to information about hardware a |
| A+(B<<16) is a 32 bit word identifying the hardware id | |||
| C is the hardware version | |||
| X+(Y<<16) is a 32 bit word identifying the manufacturer | |||
| 4+ | 0x12 | HWI a | sends an interrupt to hardware a |
| - | 0x13 | - | |
| - | 0x14 | - | |
| - | 0x15 | - | |
| - | 0x16 | - | |
| - | 0x17 | - | |
| - | 0x18 | - | |
| - | 0x19 | - | |
| - | 0x1a | - | |
| - | 0x1b | - | |
| - | 0x1c | - | |
| - | 0x1d | - | |
| - | 0x1e | - | |
| - | 0x1f | - |